The present invention relates to systems and methods for wireless data transmission. More specifically, the present invention relates to systems and methods for improving DC offset and bit timing in Bluetooth enabled wireless transceivers.
A wireless technology called xe2x80x98Bluetoothxe2x80x99 is under development to enable ease of synchronization and mobility for a plethora of corporate and consumer applications. Bluetooth technology will open up many possibilities for quick, temporary (ad-hoc) connections with colleagues, devices, or office networks. Bluetooth is described in BLUETOOTH SPECIFICATION VERSION 1.0A CORE, published in July 1999.
On the receive side, Bluetooth transceivers downconvert the received signals to baseband for further processing. One processing step involves the use of correlation algorithms to improve signal-to-noise ratio (S/N). Unfortunately, certain current Bluetooth transceiver designs offer limited performance at baseband. In particular, performance limitations have been observed with respect to clock recovery and direct current (DC) offset. Clock recovery refers to the process by which a received data stream is synchronized with a local clock to facilitate recovery of the transmitted data. DC offset at baseband is often caused by a frequency offset at the receiver relative to the transmitter. DC offset estimation is required to eliminate a residual DC signal resulting from the process of downconverting the received signal to baseband.
Hence, a need exists in the art for a system or technique for compensating for DC offset at baseband due to frequency offsets and to improve bit timing synchronization in Bluetooth enabled and other wireless transmission schemes.
The need in the art is addressed by the offset estimation and bit timing system and method of the present invention. The inventive offset estimation system includes a first circuit for receiving and correlating a transmitted signal and generating a trigger signal in response thereto. A second circuit accumulates the received signal and provides a second signal on receipt of the trigger signal. The second signal is then converted to an offset error signal.
In an illustrative implementation, the offset estimation system is implemented in a Bluetooth enabled wireless receiver adapted to receive a signal transmitted with a known bit pattern. The received signal includes a plurality of messages, each message having at least one access code and each access code having a predetermined pattern therein for at least a portion thereof. The offset estimation system analyses the bit pattern and detects the DC offset in the received signal.
In the illustrative embodiment, the first circuit includes an analog to digital (A/D) converter having a sampling rate of N samples per bit period. The A/D converter digitizes the first signal and provides a digital input signal in response to an analog reference signal. The digital input signal is next processed to provide a correlated output signal. A peak and an edge in the correlated output signal are identified and a trigger signal is provided in response thereto. In the best mode, the trigger signal is provided at a time T=N/2 after a time of identification of the peak.
The illustrative DC offset estimation system further includes a sliding window accumulator for providing an accumulated output signal. The accumulated output signal is latched and output on receipt of the trigger signal. Finally, the latched signal is used as an address to a lookup table which outputs and an error signal in response thereto. The error signal is converted to analog and used as a reference input for the A/D converter. As an alternative, the error signal may be used to adjust the signal output by an intermediate frequency downconversion stage.
In any event, the inventive system further includes a novel arrangement for providing clock recovery and bit timing with respect to the received signal. The novel bit timing system includes a first circuit for receiving and correlating the first signal with a set of weights and providing a correlated signal in response thereto. The weights are chosen to achieve the highest correlation with respect to the predetermined bit pattern in the transmitted signal. A second circuit is included for identifying a peak in the correlated signal and providing a bit timing output signal in response thereto. The bit timing output signal is then used by a data bit sampler for sampling data in the first signal.